The present invention relates to test bus architecture and more particularly to test bus architecture allowing viewing of a large number of internal signals using a small number of pins.
Integrated circuits, particularly ASICs (application specific integrated circuits), have included more and more elements in the past few years. In the past, various test points in the integrated circuits have been routed to the pins of the integrated circuit in order to facilitate testing.
However, due to the inclusion of more and more elements in integrated circuits, it has become impossible to directly connect all of the desired test points to the pins of the integrated circuits due to the limitation as to the physical number of pins available on the integrated circuit.
Accordingly, various techniques have been utilized to multiplex groups of test points so as to make them available for test purposes without requiring a separate pin for each test point. Unfortunately, the multiplexing of test points in the past has required complicated hardware arrangements on the integrated circuit which take up space on the integrated circuit and increase the cost associated with the fabrication of the integrated circuit as well as increasing its complexity.